1. Field of the Invention
The present invention relates to the field of arrays for performing logic functions. More specifically, the present invention relates to the art of providing a logic array having interleaved logic planes.
2. Description of the Related Art
Arrays for performing logic functions, typically called logic arrays or programmable logic arrays, have been used to replace random logic in many digital circuits. A programmable logic array (PLA) uses arrays of identical circuit elements to implement arbitrary logical functions in integrated circuits. A typical PLA is arranged in two portions, or arrays. The first array generates a product of sum terms and is referred to as an AND array or AND plane. The second array generates a sum of product terms and is referred to an OR array or OR plane. Typically, in NMOS technology, the AND plane and the OR plane consists of NOR arrays that are interconnected so that the first array performs a logical AND function, and the second array performs a logical OR function.
FIG. 1 shows a simplified circuit diagram of a PLA 10 having an AND plane 15 and an OR plane 20. The AND plane 15 is simplified and is represented by a row of logical AND gates 25. The actual AND plane 15 is implemented using NOR logic and a transistor arrangement well known in the art, and therefore, the simplified representation is used for clarity.
The outputs of the AND gates 25 are provided to the OR plane wordlines 30. For ease of illustration, only a small number of wordlines 30 are shown. In an actual implementation, a larger number of wordlines 30 is present. The outputs of the AND gates 25 present on the wordlines 30 are referred to as minterms (e.g., minterm1-minterm5).
The OR plane 20 also includes bitlines 35, which provide the outputs of the PLA 10. Again, for ease of illustration only a small number of bitlines 35 are shown. A clock signal is provided on a clock line 40 that is connected to the gate input of a series of p-channel transistors 45. The p-channel transistors 45 are connected between a voltage source 50 and the bitlines 35. On a low cycle of the clock signal, the p-channel transistors 45 are enabled, thus precharging the bitlines 35. A series of n-channel transistors 55 are connected between the bitlines 35 and ground 60. The gate inputs of the n-channel transistors 55 are connected to the wordlines 30. During a high cycle of the clock signal, the p-channel transistors 50 are disabled, and the n-channel transistors 55 are either enabled or disabled depending on the logic level present on the associated wordline 30. For example, if minterm1 evaluates to a true condition in the AND plane 15, the associated wordline 30 will be at a logic high, thus enabling the n-channel transistors 55 connected thereto. The n-channel transistors 55 provide a path to ground 60, thereby allowing the bitline 35 to discharge. In the example of FIG. 1, the out1 and out2 signal present on the bitlines 35 will evaluate at a logic low if the minterm1 signal is at a logic high. Output buffers 65 connected to the ends of the bitlines 35 invert the logic low to a logic high for those bitlines 35 pulled down by the n-channel transistors 55.
In an actual PLA 10, an n-channel transistor 55 may exist at each junction of a bitline 35 and a wordline 30. The PLA 10 is programmed by selectively removing certain n-channel transistors 55 during the layout of the PLA 10 to provide the desired logic output. Only the n-channel transistors 55 remaining are shown in FIG. 1.
Limitations of a typical PLA 10, as shown in FIG. 1, are described in reference to FIG. 2. FIG. 2 illustrates a simplified representation of the PLA 10 of FIG. 1. Only the wordlines 30 and the bitlines 35 are shown. The n-channel transistors 55 are represented by circles at the junctions of the wordlines 30 and the bitlines 35. FIG. 4 illustrates a truth table detailing the desired outputs from the bitlines 35 if the specified minterm on the wordline 30 is at a logic high level. Seven minterm signals are shown and six output signals are shown.
Note that each minterm controls each output line depending on the desired output signals to be provided if the minterm evaluates to true. This can cause excessive loading on certain individual bitlines 35. For example, the bitline 35 supplying the out4 signal has four loads and the bitline 35 supplying the out6 signal has five loads. As the number of loads on a bitline 35 increases, the less able the PLA 10 is to provide a reliable output. In other words, there is a practical limit to the number of loads that can be driven by a single bitline 35. If for example, that limit was 4 loads, the PLA 10 would not function properly due to the overloading of the bitline 35 supplying out6. To overcome this limitation, additional bitlines 35 must be added to spread the loading. The additional bitlines 35 related to a single output are logically ORed to provide the true output. In one implementation, 40 loads has been determined to be a practical limit. In the large PLAs 10 used in present digital applications, this loading limit is often met and additional bitlines 35 must be provided. Further compounding the problem, is the fact that the logic outputs of the PLA 10 are often changed near the end of the development cycle for the digital system employing the PLA 10, and accordingly, the PLA 10 must be designed to accommodate these contingencies. For this reason each output has multiple bitlines that are logically ORed to form the outputs of the PLA 10. Because the final design is not known, little optimization can be performed in the design of the PLA 10 and resultingly, the PLA 10 is typically oversized. This increases the footprint of the PLA 10 for a given number of minterms, thereby decreasing its density and increasing its cost. The practical limit on the number of loads depends on the specific implementation and process technology. The limit of 40 loads is provided for illustrative purposes.
One use for a PLA 10 is to provide decode logic in a microprocessor. In such an application, the inputs of the PLA 10 may represent a complex instruction set computer (CISC) instruction, and the outputs represent corresponding decoded micro-ops for that instruction. An exemplary PLA 10 providing such decode logic has approximately 30 inputs and 80 outputs. Due to the need for accommodating changes in the logic requirements, each output line has 4 complimentary bitlines 35, resulting in a total of 360 bitlines 35 to support the output lines. Such an arrangement prevents the PLA 10 from being optimized with respect to density because extra capacity must be built into the design.
FIG. 3 illustrates a physical layout diagram of the PLA 10. In the embodiment of FIG. 3, the PLA 10 has a top AND plane 70, a bottom AND plane 75, AND plane buffers 80, a top OR plane 85, a bottom OR plane 90, top OR plane buffers 92, bottom OR plane buffers 94, and output buffers 95. The height of the top and bottom portions is dictated by the height of the respective OR plane 85, 90.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above by providing a programmable logic array having multiple OR planes.